Physical IC debug – backside approach and nanoscale challenge

Physical IC debug – backside approach and nanoscale challenge

Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50– 100μm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique val...

System Reduction for Nanoscale IC Design (SyreNe)

Since 1993, the German Federal Ministry of Education and Research (BMBF – Bundesministerium füa Bildung und Forschung) runs a program for supporting applied mathematical research. Projects funded through this BMBF program on the one hand aim at solving realworld application problems while on the other hand at advancing basic mathematical research. The fifth funding period (July 1, 2007 – June 3...

No Place to Hide: Contactless Probing of Secret Data on FPGAs

Field Programmable Gate Arrays (FPGAs) have been the target of different physical attacks in recent years. Many different countermeasures have already been integrated into these devices to mitigate the existing vulnerabilities. However, there has not been enough attention paid to semi-invasive attacks from the IC backside due to the following reasons. First, the conventional semi-invasive attac...

Radio Frequency IC Design with Nanoscale DG- MOSFETs

A Petri Net Approach to Verify and Debug Simulation Models

Verification and Simulation share many issues, one is that simulation models require validation and verification. In the context of simulation, verification is understood as the task to ensure that an executable simulation model matches its conceptual counterpart while validation is the task to ensure that a simulation model represents the system under study well enough with respect to the goal...